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Qualpack TSC87251G2D
Qualification Package
TSC87251G2D / TSC83251G2D
0.5 m SCMOS3 Technology
TSC87251G2D
0.5 m SCMOS3
1999 October
TEMIC SEMICONDUCTORS IS AN ATMEL COMPANY
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1. General Information........................................................................................................................... 3 1.1 Product Description............................................................................................................................ 3 2. Technology Information..................................................................................................................... 4 2.1 Wafer Process Technology ................................................................................................................. 4 2.1.1 SCMOS3 0.5um ROM Process ................................................................................................... 4 2.1.2 SCMOS3 NV 0.5um EPROM Process ......................................................................................... 6 2.2 Product Design .................................................................................................................................. 6 2.3 Package Technology .......................................................................................................................... 6 2.3.1 Package description ................................................................................................................... 6 2.3.2 Other available packages ............................................................................................................ 7 2.4 Test .................................................................................................................................................. 7 2.5 Device Cross Section ......................................................................................................................... 8 2.6 Wafer Process Control........................................................................................................................ 9 3. Qualification .................................................................................................................................... 10 3.1 Change Procedure ........................................................................................................................... 11 3.2 Qualification Flow............................................................................................................................. 12 3.3 Wafer Process Qualification.............................................................................................................. 13 3.3.1 Process Module Reliability ........................................................................................................ 13
3.3.1.1 Hot carrier qualification.............................................................................................................................................. 13 3.3.1.2 Electromigration.......................................................................................................................................................... 15 3.3.1.3 Time Dependent Dielectric Breakdown .................................................................................................................. 16
3.3.2 Z92 Wafer Process Qualification Results ................................................................................... 18 3.3.3 Z94 Wafer Process Qualification Results ................................................................................... 19 3.4 Package Qualification....................................................................................................................... 20 3.5 Device Qualification.......................................................................................................................... 20 3.5.1 Failure Mechanisms and Corrective Actions ............................................................................... 21 3.5.2 Qualification status ................................................................................................................... 21 3.6 Outgoing Quality and Reliability ........................................................................................................ 22 3.6.1 AOQ (Average Outgoing Quality)............................................................................................... 22 3.6.2 EFR (Early Failure Rate) ........................................................................................................... 22 3.6.3 LFR (Latent Failure Rate).......................................................................................................... 23 4. User Information .............................................................................................................................. 24 4.1 Soldering Recommendations ............................................................................................................ 24 4.2 DRY PACK Ordering rules ................................................................................................................ 24 4.3 ESD caution..................................................................................................................................... 24 5. Environmental Information .............................................................................................................. 25 6. Other Data........................................................................................................................................ 26 6.1 ISO9001 Approval Certificate............................................................................................................ 26 6.2 Databook Reference ........................................................................................................................ 27 6.3 Address Reference........................................................................................................................... 27 7. Revision History............................................................................................................................... 28
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Qualpack TSC87251G2D 1. General Information
1.1 Product Description
Product Name: Function: TSC87251G2D / TSC83251G2D 8/16-bit Microcontrollers 32K EPROM / 32K ROM Z94 (SCMOS 3 NV) / Z92 (SCMOS 3) Wide range of packages including PLCC44, PDIP40, PQFP44, TQFP44, VQFP44 Multiple Hermetic Packages, Die, Wafer
Wafer process: Available plastic package types:
Other forms Locations: Process, product development Wafer plant QC responsibility Assembly
Probe test Final test Shipment control Quality Assurance Reliability testing Failure analysis
TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France GATEWAY, Philippines - ASE, Taiwan CHINTEIK, Thailand - ANAM, Korea and Philippines CHIPPAC, China TEMIC Semiconductors Nantes, France GATEWAY, Philippines - ASE, Taiwan ANAM, Korea and Philippines GLOBAL LOGISTICS CENTER, Philippines TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France
Product Quality Management Nantes Signed :
Pascal LECUYER
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2. Technology Information
2.1 Wafer Process Technology
2.1.1 SCMOS3 0.5um ROM Process Process type (Name): Base material: Wafer Thickness (final) Wafer diameter Number of masks Gate oxide Material Thickness Polysilicon Number of layers Thickness Metal Number of layers Material Layer 1 thickness Layer 2 thickness Layer 3 thickness Passivation Material Thickness 3 Ti + TiN + AlCu 300A + 600A + 5000A + 250A TiN 300A + 600A + 5000A + 250A TiN 300A + 600A + 6500A + 250A TiN CMOS (SCMOS3 - Z92) Bulk 475 m 150 mm 16
Silicon dioxide 110 A (optical - 120A electrical)
1 3000 A
SiO 2 / Si3N4 3000A / 7000 A
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2.1.2 SCMOS3 NV 0.5um EPROM Process Process type (Name): Base material: Wafer Thickness (final) Wafer diameter Number of masks Gate oxide Material Thickness Polysilicon Number of layers Thickness Poly1 Thickness Poly2 Metal Number of layers Material Layer 1 thickness Layer 2 thickness Layer 3 thickness Passivation Material Thickness 3 Ti + TiN + AlCu + TiN 300A Ti + 600A TiN + 5000A AlCu+ 250A TiN 300A Ti + 600A TiN + 5000A AlCu+ 250A TiN 300A Ti + 600A TiN + 6500A AlCu+ 250A TiN CMOS (SCMOS3 NV - Z94) Bulk 475 m 150 mm 22
Silicon dioxide 110 A (optical - 120A electrical)
2 2000 A (amorphous) 3000 A (polysilicon)
SiO 2 / Nitride Oxide 3000A /15000 A
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2.2 Product Design
Die size Pad size Logic Effective channel length Gate poly width Gate poly spacing Metal 1 width Metal 1 spacing Metal 2 width Metal 2 spacing Metal 3 width Metal 3 spacing Contact size Via 1 size Via 2 size For TSC87251G2D: 17.84 mm2 (4250 m * 4400 m) For TSC83251G2D: 17.84 mm2 (4250 m * 4400 m) 84 m * 84 m 0.42 m 0.5 m 0.6 m 0.6 m 0.7 m 0.8 m 0.7 m 0.8 m 0.7 m 0.6 m 0.6 m 0.7 m
2.3 Package Technology
2.3.1 Package description Depending on the customer's need. For information, the following data concern the PLCC 44. Package weight Chip separation method Lead frame Material Thickness Size Lead plating Die attach Material Type Wire bonding Material Diameter
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2.34g Sawing Cu 10 mils 270*270 mils 2 Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMIS Gold 33um
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Method Molding Material Flammability rating Marking Method Coding example Thermosonic Sumitomo EME 6300HS UL94V-0 Printed ink T optional special customer marking TSC83C51RB2-MCA (c) INTEL 80,82 Date-code Lot nbr No Tube Antistatic PVC 27 Box Cardboard 972 Device type, Quantity, Date Code, Production code Code 39 to EIA-556-A
Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labeling (minimum) Bar coding 2.3.2 Other available packages PQFP, PDIP, CQFP, CERDIP TQFP, VQFP
No dry pack required Dry pack required
2.4 Test
Probe equipment Probe temperature Test equipment Test temperature Commercial range Industrial range Automotive range SCHLUMBERGER ITS9000 / S15 85C SENTRY 15
25C 25C and optional 85C 25C, 125c and optional -40c
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2.5
Device Cross Section
2
Final Z92 Cross Section
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2.6 Wafer Process Control
All the inspections and controls are defined as a process step in the production management software, and are led by using a centralized SPC software. PC system could be summarized as follows:
Engineering Database
Wafer Fab
Probe
die-sort
Assembly
Final Test
- NANTES: hermetic packages - Subcontractors : plastic packages Process parameters Electrical Test
- NANTES : hermetic packages - Subcontractors : plastic packages
Physical SPC (xbar / R) Cpk tracking
Electrical SPC (xbar / s) Cpk tracking
Attribute
Physical measurement SPC (xbar / R) Cpk tracking
Attribute Measurement
Critical process parameters are identified by using F.M.E.A. and other advanced tools. Those parameters are followed in real time with the SPC methodology and their capability is measured and monthly reported in the Operation Review. For end 1999, the Cpk target is the following:
% of all parameters per Cpk categories
100% 80% 60% 40% 20% 0% 1995 1996 1997 1998 Obj. 99 >1.67 <1.67
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3. Qualification
Product Qualification
Wafer Process Qualification
Package Qualification
Device Type (Design) Qualification
All product qualifications are split into three distinct steps as shown above. This same procedure is also used to qualify a change. Before a product is released for use, it must have been manufactured using a qualified wafer and package process. Before a device is released for production processing, it must also have successfully completed its required specific qualification. The standard tests which are used for this procedure are shown in the section "Qualification Flow" .
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3.1 Change Procedure
All changes are controlled by PCN (Product Change Notice). All major changes are notified to the customers affected by the change. A major change is defined as a change that requires evidence of no electrical, mechanical impact on the product, or a change in the specification or marking of the product or packing. The list of changes usually considered as major is detailed hereafter:
1 1-1 1-2 1-3 1-4 1-5 1-6 2 2-1 2-2 2-3 2-4 2-5 3 3-1 3-2 3-3 3-4 3-5 4 4-1 4-2 4-2 4-3
General Major Changes Manufacturing line Sequence of fabrication process cycle Material type Electrical parameter External physical dimension Die size Changes specific to wafer fabrication area Doping method Gate oxide formation method Equipment change Layer Thickness Module dimensions Changes specific to to assembly process area Sawing method Die attach Wire interconnect tools Molding process Tinning method Changes specific to test area Specification limit Test coverage reduction Product identification Final conditioning
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3.2 Qualification Flow General Requirements for Plastic packaged CMOS IC
Standard Test Description Electrical Life Test (Early Failure Rate) 12 hours 150C (Tj) 5.75V Electrical Life Test (Latent Failure Rate) 1000 hours 150C 5.75V Dynamic or Static Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses Latch up 50mW power injection 125C NV Memory Dataretention High Temperature Storage 165C Temperature Cycling 1000 cycles -65C/150C air/air Pressure Pot after Mounting Stress 168 hours 130C/85%RH 85/85 Humidity Test 1000 hours 85C/85%RH HAST 336 hours 130C/85%RH/5.5V Moisture Sensitivity Ranking Infra Red Stress 220C/235c/3 times Solderability Qualification type (acceptance) Device (1/2000 12h) Device (0/100 500h) Device (0/3 per level) Device (0/10) Device (0/50 500c) Die and Package (0/50 500c) Die and Package (0/50 168h) Die and Package (0/50 500h) Die and Package (0/50 168h) Package (0/10 per class) Package (0/3) Package (0/5)
MIL-STD 883D Method 1005 MIL-STD 883D Method 1005 MIL-STD 883D Method 3015.7 JEDEC 78
MHS PAQA0046 MIL-STD 883D Method 1010 MHS PAQA0184 EIA JESD22-A101 EIA JESD22-A110 EIA JEDEC J-20-STD MIL-STD 883D Method 2003 MIL-STD 883D Method 2015
Marking Permanency
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3.3 Wafer Process Qualification
3.3.1 Process Module Reliability This chapter contains all the information relative to the reliability of the SCMOS3 technology. Results presented in the following sections concern the reliability of the basic process steps that build up the technology.
3.3.1.1 Hot carrier qualification
STATIC NMOS DEGRADATION
Channel length in m Process corner Substrate current in A/m VD=5.5v, VG=2.25v Substrate current in A/m VD=3.6v, VG=1.6v Lifetime in seconds for 10% shift of Gm at VD=5.5v Lifetime in seconds for 10% shift of Gm at VD=3.6v
0.5 Fast 17 0.35 3.2e3 8e7
0.55 Fast 15 0.3 3.7e3 10e7
0.6 Fast 13.4 0.25 4.2e3 12e7
0.65 Fast 12.1 0.22 4.7e3 14e7
0.7 Fast 11.1 0.2 5.2e3 16e7
0.5 Typical 14.7 0.3 3.8e3 10e7
STATIC PMOS DEGRADATION
Channel length in m Process corner Substrate current in A/m VD=5.5v, VG=2.25v Substrate current in A/m VD=3.6v, VG=1.25v Lifetime in seconds for 10% shift of Gm at VD=5.5v Lifetime in seconds for 10% shift of Gm at VD=3.6v
0.5 Fast 0.31 2.3e-3 2.7e4 2e7
0.55 Fast 0.28 1.9e-3 3.1e4 2.5e7
0.6 Fast 0.25 1.6e-3 3.5e4 3e7
0.65 Fast 0.22 1.4e-3 3.9e4 3.8e7
0.7 Fast 0.21 1.1e-3 4.3e4 4.6e7
0.5 Typical 0.24 1.6e-3 3.5e4 3.2e7
EXPERIMENTAL RESULTS IN DYNAMIC MODE: hot carrier degradation effects on inverter propagation time have been measured on oscillators running at 75 MHz at 7v and 6.5v. Accelerator factor in voltage is then carried out and expected degradation laws at 5v and 3.3v derived. The following graphs show the frequency degradation of oscillators running at 5v and 3.3v.
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SCMOS3 Frequency degradation
VCC = 5 Volts.
20
DFreq/freq in %
15
200 MHz
10
100 MHz 50 MHz 25 MHz
5
0 0 5 10 15 20 25 30
Years
SCMOS3 Frequency degradation
VCC = 3.3 Volts.
1 0,8
DFreq/freq in %
200 MHz
0,6 0,4 0,2 0 0 5 10 15 20 25 30
100 MHz 50 MHz 25 MHz
Years
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3.3.1.2 Electromigration
Characterization Stresses of electromigration are achieved for 1000 hours on 32 packaged metal line running on flat with a current density of 2x106 A/cm2 at a temperature of 200C. Lines are declared to be failed for a shift of the initial resistance by 20%. Results are summarized in the table below.
Level Metal1 Metal2 Metal3
W/L/T(1) 2/2000/0.50 2/2000/0.50 2/2000/0.70
Structure Ti/TiN/AlCu/TiN Ti/TiN/AlCu/TiN Ti/TiN/AlCu/TiN
Failures No No No
(1)W/L/T=Width/Length/Thickness of the metal line in microns
Lifetime projection The objective of reliability is to reach less than 10FIT on metal line within 10 years at a temperature of 150C. As no failures have been found at 1000 hours in the above stress conditions a lifetime projection in FIT is meaningless. However, assuming for AlCu metalization an activation energy in temperature Ea of 0.60eV and an activation in current with a power-law coefficient n of 2, the current density which guarantees no failures within 10 years at 150C can be extrapolated. With these assumptions the projected current density for no failures at 150C within 10 years is calculated as 5x105A/cm2 which is much higher than the current density of 2x105 A/cm2 specified in the design rules.
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3.3.1.3 Time Dependent Dielectric Breackdown
QBD MEASUREMENT: The critical charge, supported by the thin oxide and related to the extrinsic and intrinsic defects, is measured on TOX/P- and TOX/N- capacitors. The tested capacitor areas are varying from 4e-4 to 5e-2 cm2. Two types of capacitors with poly overlaping the field oxide (DEC) and poly non overlaping the field oxide (INC) are measured. The distributions have been obtained from 750 measurements for each area and type of capacitors on 10 different lots. Extrinsic defects: The two graphs here after represent the % of failures vs area for Qbd below or equal to 0.1 Cb/cm2. The law of Poisson is used to determine the D0 defect density of the extrinsic defects: Y=1-exp(-Area * DO) Poly overlaping the Field oxide on Tox/P- and Tox/N-: The DO is found to be 1.1 def/cm2. This result is in agreement with the goal for D0 of 1 def/cm2.
Qbd < 0.1Cb/cm
CAPA WITH POLY OVERLAPING THE FIELD OXIDE
0
-0,02
DEC PDEC NPoisson
Ln(1-Y)
-0,04 -0,06 0 0,02 0,04 0,06
Area in cm
DO=1.1 def/cm
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Poly non overlaping the Field oxide on Tox/P- and Tox/N-: The DO is found to be 0.9def/cm2. This result is in agreement with the goal for D0 of 1 def/cm2.
Qbd < 0.1Cb/cm
CAPA WITH POLY NON OVERLAPING THE FIELD OXIDE
0
-0,01
Ln(1-Y)
-0,02
INC PINC N-
-0,03
Poisson
-0,04
-0,05 0 0,02 0,04 0,06
Area in cm
DO=0.9 def/cm
Intrinsic defects: The graph here after represents the percentage of failure for a Qbd > 10 Cb/cm vs the area. The worst case given by the bigest capacitors shows that 67% of the total distribution has a Qbd > 10 Cb/cm. This result guarantees a good reliability behaviour. The critical charge, supported by thin oxide and related to the extrinsic defects, is measured on TOX/P- capacitors of 42570um2 and TOX/N- capacitors of 85140um2. Following are the average results obtained on recent lots from a distribution of about 60 sites per wafer. The minimum specification limit is 10C/cm2.
Qbd > 10 Cb/cm
SCMOS3 PROCESS
1
0,9
0,8
DEC PDEC N-
Yield
0,7
INC PINC N-
0,6
0,5 0 0,02 0,04 0,06
Area in cm
Conclusion: The QBD results demonstrate high reliability level of SCMOS3 thin oxide.
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3.3.2 Z92 Wafer Process Qualification Results This section summarizes the cumulated reliability data of 0.5um microcontrollers ROM technology.
Lots Z27746A Device Type TSC251G2D Test Description EFR Dynamic Life Test LFR Life Test Step 12h 500h 1000h 12h 500h 1000h 12h 500h 1000h 12h 500h 1000h Result 3/2661 0/100 0/100 11/11712 Contacts alignment 0/699 0/699 5/7318 0/200 0/200 3/2238 0/173 0/173 Passivation scratch Poly particle Silicon breakdown Comment Poly particle Metal3 defect
Z27735A Z29249 Z29683C Z29936 Z27300A Z27880A Z28109A
TS80C32X2
EFR Dynamic Life Test LFR Life Test
TS83C51RC2
EFR Dynamic Life Test LFR Life Test
Z26274A Z26407 Z27291A
TS83C51RX2
EFR Dynamic Life Test LFR Life Test
Global
All products
EFR Dynamic Life Test Commercial / Industrial Automotive (1)
12h 24h 168h 500h 1000h
22/23929 919 ppm (828 ppm / 10 mm2) 0/3564 0ppm 0/1172 0/1172 0/1172 4.7 fit (3.0 fit / 10mm2)
LFR Life Test
Note (1): The additional operations included in the automotive backend flow allow to reduce significantly the Early Life Failure Rate. As long as needed to achieve the Automotive Quality Assurance requirements, these operations may be any of those described hereafter: 18
Statistical wafer sort Accelerated Dynamic Burn-in at probe Probe critical parameters 3 sigma sort Part Average Testing Dynamic Burn-in of products Other equivalent methods
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3.3.3 Z94 Wafer Process Qualification Results This section summarizes the cumulated reliability data of 0.5um microcontrollers EPROM technology.
Lots Z27314A Z27748 Device Type Test Description Step 12h 24h 500h 12h 24h 500h 1000h 12h 24h 500h 1000h 12h 24h 500h 1000h 12h 24h 500h 1000h Result 4/3772 0/360 1/150 1/1663 0/323 0/100 0/97 8/11533 0/1284 0/500 0/500 2/953 0/324 0/100 0/100 2/2333 0/297 0/100 0/100 Comment Poly bridging, Interlayer oxide defect, functional not identified, metal 2 photo etch bridging Functional not identified
TSC87251G2D EFR Dynamic Life Test LFR Life Test
Z28233C
TSC87C51RB2 EFR Dynamic Life Test LFR Life Test
Z28090B Z28987 Z29142 Z29311D Z29568B Z28303C
TSC87C51RC2 EFR Dynamic Life Test LFR Life Test
Poly particle Contact misalignment Capacitor oxide defects
TSC87C51RD2 EFR Dynamic Life Test LFR Life Test
Poly particle
Z28430A
TSC87C52X2
EFR Dynamic Life Test LFR Life Test
Functional not identified
Global
All products
EFR Dynamic Life Test Commercial / Industrial Automotive (1)
12h 24h 168h 500h 1000h
17/20254 839 ppm (705 ppm / 10mm2) 0/2588 0ppm 0/950 1/950 0/797 14.2 fit (11.6 fit / 10mm2)
LFR Life Test
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3.4 Package Qualification
This section summarizes the initial package qualification data of TSC87251G2D and TSC87251G2D products in PLCC44.
Lots Z27314A Device Type Test Description Step 500h 1000h L1 15c 168h 500c 1000c 15c 168h Result Comment 0/50 0/50 0/10 0/50 0/50 0/50 0/50 0/50 0/50
Z27746A
TSC87251G2D 85/85 Humidity PLCC44 Moisture Sensitivity Ranking HAST after Soldering Stress TSC83251G2D Thermal Cycles PLCC44 HAST after Soldering Stress
Pass level 1 of J-20-STD
3.5 Device Qualification
This section presents the qualification results of TSC87251G2D/TSC83251G2D devices.
Lots Z27314A Device Type Test Description Step 12h 24h 168h 500h 1000h 500h 1000h 12h 24h 168h 500h 1000h Step 2000V Result Comment 2/1978 Interlayer oxide defect 0/360 Polysilicide particle 0/150 1/150 Metal 2 photo etch bridging 0/50 0/50 3/2661 Polysilicide particle 0/211 Metal 3 defect 0/100 0/100 0/100 Result Comment 3/3 Class 1 of MIL883
TSC87251G2D EFR Dynamic Life Test PLCC44 LFR Life Test High Temp. Retention
Z27746A
TSC83251G2D EFR Dynamic Life Test PLCC44 LFR Life Test
Lots Z26629
Device Type
Test Description
TSC87251G2D ESD HBM Latch up Overvoltage Power injection TSC83251G2D ESD HBM Latch up Overvoltage Power injection
Z27746
10V 50mW 2000V 3000V 10V 50mW
0/5 0/5 0/3 0/3 0/5 0/5
Latch-up free Class 2 of MIL883
Latch-up free
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Comments: No reject observed during package qualification tests. One reject in LFR, but physical analysis demonstrated the failure was wafer process dependant and not related to the device itself. As a consequence it was not charged for device qualification. 3.5.1 Failure Mechanisms and Corrective Actions As part of TEMIC continuous improvement policy, all defects are analysed. For all failure mechanisms identified, root causes ranked regards number of occurencies and criticity are investigated and addressed by corrective actions.
Failure Mechanism 56% Contacts misalignment 26% Poly defects Root Cause RTA drift Corrective Action Upgrade of RTA equipment # Hard mask : replacement of PR Titane mask by masking buffers during Ti deposition for # polysilicideBARC (Bottom Anti-Reflective Coating) # PR strip optimization Date 06/99 Effect reduce alignment scattering Reduction of defect density at Poly level Check of Efficiency Visual inspection, yield - 07/99 Yield EFR - 12/98
Defect density at Poly level
10/98
Improve Poly dimension control 03/99 Defect density reduction Reduction of the defect density
Yield EFR - 12/98 EFR - 05/99
6% Metal particles
PR strip process
# PR strip method optimized # Equipment upgrade (Semitool)
03/99 07/99
Yield - EFR 05/99
6% Passivation 6% Silicon breakdown
Marginal Marginal
3.5.2 Qualification status The 0.5um logic wafer process was qualified on 1997 September. The qualification was extended to OTP microcontrollers (SCMOS3 NV) process on 1999 April. The TSC83251G2D was qualified on 1999 January, and OTP version TSC87251G2D was full qualified on 1999 April.
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3.6 Outgoing Quality and Reliability
3.6.1 AOQ (Average Outgoing Quality) The AOQ is measured following 100% test by sampling outgoing product. The results of this inspection are recorded in ppm (parts per million) using the method defined in JEDEC 16. The figures below cover the last years for both the subject and structurally similar products.
40
30 ppm
20
10
0 1995 1996 1997 Year 1998 Obj.99
3.6.2 EFR (Early Failure Rate) The EFR is measured on a sample of devices by operating them at an elevated temperature and measuring the number which fails to meet specification after 12 hours at 150C. The figure is expressed in terms of ppm.
800 600 ppm 400 200 0 1995 1996 1997 Year 1998 Obj.99
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3.6.3 LFR (Latent Failure Rate) The LFR is measured by operating devices at elevated temperatures for 1000 hours and measuring the failure rate. Using the Arrhenius law, the expected failure rate at a operating temperature of 55C is calculated using an activation Energy of 0.6 eV with a confidence level of 60%. This is expressed in units per billion hours (FIT). The figures given are for the subject and structurally similar products.
40
30 FIT
20
10
0 1995 1996 1997 Year 1998 Obj.99
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4. User Information
4.1 Soldering Recommendations
For DRY PACKED products, TEMIC recommends to strictly follow the procedure described hereunder: - Dry packed products must not be stored more than 1 year at 40c - 90%rh (worst storage conditions assumed) - A longer storage period is allowed taking into account the following conditions: 5 years max at 25c (+/-5c) - 50%rh - From opening of the packs, the product must be assembled within 48 hours. (worst in-process storage condition assumed: 30c - 60%rh) - If they cannot be soldered within this time period, then the pieces must be dryed at 125c for 24 hours. Only one drying is allowed. - Max relative humidity allowed in the bag is 20% (readable on the indicator inside the bag). If this value is reached, then the parts must be dryed at 125C for 24 hours before mounting. - For high sensitive products, the delay between pack openning and assembly is reduced to 6 hours (Level 6 of JEDEC 22-A112). In this case, a warning printed on each pack advises the user of this restriction.
4.2 DRY PACK Ordering rules
TEMIC qualification procedure allows to classify products according to JEDEC 22-A112 and to determine the convenient conditioning for safe customer use. Nevertheless, even if the product is not classified as moisture sensitive, it is possible (for example if storage conditions are not properly controlled) to order product with a Dry Pack.
4.3 ESD caution
The user must protect components against EOS and ESD damages by grounding personal and workstations.
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5. Environmental Information
The TEMIC Environmental Policy aims are : - Reducing the use of harmful chemicals in its processes - Reducing the content of harmful materials in its products - Using re-cyclable materials wherever possible - Reducing the energy content of its products As part of that plan, Ozone Depleting Chemicals are being replaced either by TEMIC MHS or its subcontractors' process.
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Qualpack TSC87251G2D 6. Other Data
6.1 ISO9001 Approval Certificate
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6.2 Databook Reference
The datasheet is available upon request to sales representative, or on TEMIC Semiconductors web site: http://www.temic-semi.com
6.3 Address Reference
All inquiries relating to this document should be addressed to the following: TEMIC Nantes MHS S.A. BP70602 44306 Nantes Cedex 3 France Telephone (33) 2 40 18 18 18 Telefax (33) 2 40 18 19 00 Or Direct contact Pascal LECUYER Quality Engineer Telephone (33) 2 40 18 17 73 Telefax (33) 2 40 18 19 00
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7. Revision History
Issue 0 Modification Notice Initial Product Qualification Report Application Date 1999 October
Remarks: The information given in this document is believed to be accurate and reliable. However, no responsability is assumed by TEMIC for its use. No specific guarantee or warranty is implied or given by this data unless agreed in writing elsewhere. TEMIC reserves the right to update or modify this information without notification, at any time, in the interest of providing the latest information. Parts of this publication may be reproduced without special permission on the condition that our author and source are quoted and that two copies of such extracts are placed at our disposal after publication. Before use of such reproduced material the user should check that the information is current. Written permission must be obtained from the publisher for complete reprints or translations.
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